Sequential decision making device



Dec. 28, 1965 J. E. GAFFNEY, JR

SEQUENTIAL DECISION MAKING DEVICE 12 Sheets-Sheet 1 Filed Oct. 19. 1960DECODER MEMORY ADDRESS NODE NETWORK MAGNETIC CORE MEMORY WORD OUTPUT OFRECORD BEING READ WORD INPUT OF RECORD BEING WRITTEN SOURC I AE 06mmTIII HR ME 6 NODE NETWORK CONTROL ZIO READ

WRITE RECORD ADDRESS mmvron.

JOHN E. GAFFNEY, Jr. m

JA TTOR N5 14 FIG.2

1965 J. E. GAFFNEY, JR 3,225,683

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19. 1960 12 Sheets-Sheet 2NODE OUTPUT LINES TO MEMORY ADDRESS DECODER i 3 m I IH" 0 mm a? I H. w(n O Q O 2 Dec. 28, 1965 J. E. GAFFNEY, JR

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19. 1960 12 Sheets-Sheet 3s 40. 402 FIG.4

A 8| SAY s52 409 408 OUTPUT TO l a OR 405 5x 53 OR NEXTLEVEL (Niy setNiz set) L I x L Nix set 0R 5 I- 57' T B a 407 L AY SAZ 4|4 415 (4B 5LE: 8 0R (Nly sel NIZ set) 4'5 E 5 4|? E 5 s" m C a BX 8 x x SAY A2 Q lL T I Hi 0R (Nly set +N|z set) F I NODE OUTPUT LINE k I REAQ |E\ 1 i IREsgT 4:0 FFS NODE Nix H6 5 s 502 MAKE Nix BUSY 509 A a I HOLD GOAL A Y51 503 504 SEX 506 508 a 8 OR a OUTPUT T0 (Niy set -51 set} NEXT LEVELDec. 28, 1965 J. E. GAFFNEY, JR 3,226,683

SEQUENTIAL DECISION MAKING DEVICE Filed 001.. 19, 1960 12 Sheets-Sheet 4ADVANCE TO NEXT LEVEL INDICATOR TURN ON LEVEL i SC INDICATOR 0%; nodew'ndin s say at x 8 wa e node wmamgs 1 x Niz sel C)( other noflewinflings 1.

l l-il NODE FIG?! ARRAY Dec. 28, 1965 Filed Oct. 19. 1960 J. E. GAFFNEY,JR

SEQUENTIAL DECISION MAKING DEVICE 12 Sheet s-Sheet 5 F|G.8u

F none 1-1 7 8M] I 8l0 8N\ 8l2 M ODE mzuomr MEMORY MESSAGE BEING READ!ADDRESS ADDRESS I L 1 A memo DECODER REGISTER MESSAGEbemqRECEIVE SHBIJAKEMITECYCLE r L NODE NOD L READ I I usrw nx WRITE CONTROL 1 i r "1 1-i0A ,mooc 1-0 LMESSAGEbemqTRANSMITTED 848' k i L 847 I m3 824 l s g J ILIAISEMLRITE CYCLE A A L l 1 846 NODE 823 04-0 3 s22 1 gmpnffiobirmamINPUT lwono LINE 1 DATA REGISTEn E WORD READY I 827 SUI Mom ENDofHESSAG:

1o BUFFER SENSOR 'READY I REGISTER L J u 4 828 3 g 830 I PUT WORD INPUTNOD52 2; LINE ADDRESS LINE N am REGISTER LOGIC REGISTER I To EFQTER 5s32 83| 1:1 2 OUTPUT I I I 0 i LINE I DATA REGISTE 1852 g comm.

s02 Lssm I 9 FROM BUFFER REG'STER cHARAc'TER TRANSMITTEII' a {READ CYCLEREQUEST j L MESSAGE REA Y i 54 OJTPUT I LINE N DATAREGISTER FROM BUFFERREGISTER Dec. 28, 1965 J. E. GAFF NEY, JR

Filed Oct. 19, 1960 12 Sheets-Sheet 6 iROM iNPUT LINE DATA REGISTERS 8 bI 19 OUTPUT LINE DATA REGiSTERS 307i, 808 l:: 839 B520 84') MAGNETBUFFER ENDofMESSAGE CORE SENSOR MEMORY Jane REGISTER e40 1 & g EOM T 819L 837 A B READ CYCLE CONTROL DATA s20 WRITE CYCLE CONTROL A 6 J49 Reuestin Lmeldenflflcotion mom curglgorRequesis I DATA "/83? g 838 B48WRITE CYCLE READ CYCLE & END ofMESSAGE flflequesi Scanner RequestScanner SENSOR 850 I La 50M 5 v 822 844 Model-I OUTPUT LINE WRITE odeZ-IADDRESS SELECT 842 o Node N-I & Q I 845J 8555] INPUT LINE READ ADDRESSssuacr 835 READ LINE ADDRESfi f LINE ADDRESS i SCAN FOR INPUT MESSAGE 483i ao3/ FIGBC 3 8b Dec. 28, 1965 J. E. GAFFNEY, JR 3,225,533

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19. 1960 12 Sheets-Sheet 8PROGRAM ARRAY l20| PROGRAM CONTROL DATA ENTER STAGE SELECT DRIVE SHIFTREGISTER FIG.|2

1965 J. E. GAFFNEY, JR 3,226,683

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19. 1960 12 Sheets-Sheet 1OSTAGE t, STAGE 1, INPUT BUSES OUTPUT BUSES S INPUT S INPUT S OUTPUT SOUTPUT I40 Inhibit TASK A-fi COMPLETED STAGE SELECT 8| is! NODE SELECTDec. 28, 1965 J. E. GAFFNEY, JR 3,226,683

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19. 1960 12 Sheets-Sheet 11l505/ START FUNCTION A-h L REQUEST 1 PREF.

1502} SA 2'! 5 L PREF INHIBIT PROCEED CLAMPS OF THE 2nd PREFERENCESUBNODE TASK A-T COMPLETED 4 75 kg? I STAGE n SELECT i'l' 2nd PREFERENCEi NODE SELECTED f f Dec. 28, 1965 J. E. GAFFNEY, JR 3,226,633

SEQUENTIAL DECISION MAKING DEVICE Filed Oct. 19, 1960 12 Sheets-Sheet 12A T3 I606 I605 R L JXECUTE T3 1 NWT EXECUTE T2 1 lag,

as: |6l3 60' TI EXECUTE FUNCTION A of TI ,TO NOdEAT To d 6'4 A-T |6l8START FUNCTION 2 EART FUNCTION \A-I A-T s 2 ISIS) E E T START FUNCTION Al IBIO/ i START FUNCTION 1 START FUNCTION A4 REQUEST A42 REQUEST FIG. l6

United States Patent 0 3,226,683 SEQUENTIAL DECISIGN MAKING DEVICE JohnE. Gaii'ney, Jr., Briarciiif Manor, N.Y., assignor to InternationalBusiness Machines Corporation, New York, N.Y., a corporation of New YorkFiled Oct. 19, 1960, Ser. No. 63,631 15 Claims. (Cl. 340-1725) Thisinvention relates to logic circuits and more particularly to asequential decision making logic circuit.

In many computer applications it is necessary to produce a plurality ofcontrol voltages for controlling the operation of the computer. Thesecontrol signals must be produced in a certain sequence and the sequencemust be reproducible.

As an example, a magnetic core memory addressing circuit must produce aplurality of control voltages for gating the various words of aparticular record into particular storage locations in the memory. Thesequence of these control voltages must be reproduced when it is desiredto read the record out of the memory so that all words of the record areread out in the correct sequence. Further, the addressing circuit musttabulate available storage locations in the computer memory so that arecord which is to be written into the memory is gated to an availablestorage location. The problem of tabulating available storage locationsin a computer memory and assigning addresses in such a manner that aprescribed distribution of data in the memory unit is assured has longbeen recognized as an important one.

In a particular system it may be desirable that data of a given categorybe stored in a prescribed segment of the memory and in another system itmay be desirable that all data be distributed uniformly throughout thememory since all data is of a given category. In such a case, all of thedata should not be concentrated in clusters about particular addresses.Normally, the operation of a memory unit is so programmed that atabulation of available storage locations is maintained and there is aprescribed set of rules which is applied in choosing a particularstorage location from the list of available ones. In such anarrangement, storage space is wasted in maintaining the tabulation ofavailable storage locations. It would be desirable for the memory unitto accept a piece of data and file it without having the particularstorage designation assigned by either the programmer or by a compilerroutine. Such a memory unit would be structured so that it could begiven some choice in finding a storage location. In such a unitaddresses or storage locations would be assigned to a sequence of inputsby means of a sequence of choices where one choice is assigned to eachword of the input.

Another application in which control signals must be produced in acertain sequence is the operation of a butler storage unit whichoperates between several data transmission lines and a digital computerwhich both receives data from these lines and transmits data out of thecomputer on the lines. Many prior art digital computers have operated onthe fixed word length principle so that a butler storage unit having adefinite number of storage locations is provided between eachtransmission line and the digital computer. However, many digitalcomputers now operate on a variable word length technique so that it isnot desirable to provide a bulTer storage unit of a definite number ofstorage locations between each transmission line and the digitalcomputer. If this were done, a great number of storage locations wouldbe wasted since each butler unit would have to have as many storagelocations as the maximum number of words possible in each record. Underthese circumstances, it is desirable to provide a single bufier unitbetween all of ice the data transmission lines and the digital computerand to assign storage space in the butter in a manner such that thebuffer can service all of the lines.

Another computer application in which a number of specific sequences ofcontrol voltages are required is in programming the tasks which are tobe performed by a digital computer. Many digital computers now have alarge number of units connected in the system. For example, a digitalcomputer may have several input'output units, several memory units andseveral arithmetic and logical units. Many times it is not necessary toutilize all of these units in carrying out a particular program. Undersuch circumstances it may be possible to simultaneously perform severalprograms it a control device can be provided to sequence the tasks whichare to be performed by the computer. Such a control device must becapable of determining which units are available for performing a giventask and must be capable of establishing preferences in performingparticular tasks between the various programs.

Accordingly, it is an object of the present invention to provide asequential decision-making device for controlling the operation of adigital computer.

It is another object of the present invention to provide a node networkin which connections can be made between various nodes so that the nodessequentially control the operation of a digital computer.

It is another object of the present invention to provide a memoryaddressing circuit which gates input words to available memory storagelocations without maintaining a tabulation of available storagelocations.

It is another object of the present invention to provide an improvedmemory address circuit in which extra storage space need not be used forthe tabulation of available storage locations.

It is a further object of the present invention to provide a controlsystem for a butler storage unit so that a single buffer storage unitcan be used between a plurality of data transmission lines and a digitalcomputer.

It is a further object of the present invention to provide an improvedbulfer storage unit for variable word length computer systems.

It is a further object of the present invention to provide a sequentialtask-ordering device for use with a digital computer having a number ofoperating units capable of performing certain tasks.

It is a still further object of the present invention to provide asequential task ordering device which controls the operation of adigital computer so that several programs can be carried onsimultaneously in the computer.

These and further objects and advantages of the present invention willbecome more apparent from the following description and appended claimstaken in conjunction with the drawings in which:

FIGURE 1 is the diagrammatic showing of a node network used foraddressing a memory;

FIGURE 2 is a block diagram of a memory addressing system;

FIGURE 3 is a block diagram of two levels of the node network;

FIGURE 4 is a logic diagram of a single node in the node network;

FIGURE 5 is a logic diagram of a modification of the node network;

FIGURE 6 is a circuit diagram of one embodiment of the single node;

FIGURE 7 is a diagrammatic representation of a buffer storage unit for adigital computer;

FIGURE 8a is a portion of a block diagram of a butler storage system;

FIGURE 8!] is another portion of the block diagram of a butler storagesystem;

FIGURE 80 shows the manner in which FIGURES 8a and 8b fit together;

FIGURE 9 is a diagrammatic representation of a sequential task-orderingdevice for a digital computer;

FIGURE 10 shows task sequences for a digital computer;

FIGURE 1 la shows a service request array for a digital computer;

FIGURE llb shows a control array for a digital computer;

FIGURE 12 shows a block diagram of the program array;

FIGURE 13 shows a block diagram of the service request-control array;

FIGURE 14 shows a circuit diagram of a sample subnode in the programarray;

FIGURE 15 shows a circuit diagram of another portion of the programarray; and

FIGURE 16 is a circuit diagram of the service request-control array.

In accordance with one embodiment of the invention a self-addressingmemory is provided which completely relieves the programmer of thesometimes arduous task of maintaining tables of available andunavailable memory locations. With this device, provided sufiicientspace remains in the memory to accommodate a given record, this recordcan be written into the memory without specification of the particularlocations into which it is to be written. The only address associatedwith this record is an identification number or other name by which itcan be referred to subsequently.

By means of this device, certain areas of memory can be given greaterpreference for selection as storage space than other areas for a givenrecord or class of records. This feature could be used to facilitate aclustering of selected addresses. around a given address according to aprescribed probability distribution function such as a normal or auniform distribution. Further, when used with the general store of acomputer, certain areas of this general store could be allocated forparticular uses, such as [/0 area, intermediate results area, etc.Although a particular area would normally be bounded, in the case ofmaximum demand for space in this area, addresses in other areas would beselected by the address ing device. That is, there is probability that agiven address distribution might extend into other areas. For example,if a uniform distribution on a certain group of address were assumed,this distribution might extend into other areas. These areas correspondphysically to the tails of the distribution curve. Therefore, if therewere an excess demand for space in this area, locations in other areaswould be sought until the entire record to be stored was actuallystored.

The self-addressing memory consists of two units, the store which couldbe a conventional core memory, and an address control unit. Thisinvention is directed particularly toward this address control unit. Thefunctions of these two units can be incorporated into one physical unitof equipment.

The address control unit is a two-dimensional array of nodes, certainones of which can be electrically linked together to form a chain. Eachnode of the address control unit corresponds to either one or a block ofwords in the memory. Corresponding to every record stored in the memory,there exists one such chain of nodes, one node for each one, or a blockof, words in the record. Upon writing, or entering, the record into thememory, a connection is propagated among the nodes, one after the other,until all of the record has been entered into storage. This connectionis propagated from an initiating node according to the preferenceselection roles built into the array. This record is identified, for thepurposes of later readout, by the particular initiating node, or source,with which it is associated. The address or name" of this source is thesole identification required for the entire record. An actual electricallinkage among the nodes forming the chain for any given record ismaintained throughout the lifetime of this record in the storage device.This linkage can be disrupted or destroyed upon a signal from thecontrol circuitry associated with the address control unit.

In accordance with other embodiments of the invention, a similar arrayof nodes is used to control a buffer storage unit for a digital computerand an array of nodes is used to control the performance of tasks byparticular units of a digital computer.

Referring to FIG. 1 there is shown a diagrammatic representation of anode network. Such a node network is made up of a plurality of sources,sources 13 being shown, and a number of individual nodes, nodes 442being shown.

Each record which is to be stored in the memory is associated with aparticular source, for example, source 1, designated S A sequentialconnection is then established between a number of nodes, one node beingenergized for each word in the record, or one node being energized foreach group of words in the record. Each node is associated with aparticular storage location in the memory unit and cnergization of thatnode allows a particular word to be entered into that particular storagelocation.

The various nodes are divided into levels. The first level, designated1', comprises node 4, N node 5, N and node 6, N Similarly, the secondlevel, designated j, includes nodes 7, 8 and 9 and the third level,designated level k, includes nodes 10, 11 and 12.

A path or connection through an array of this nature might beestablished as follows:

( ia? 3 kx That is, the connection is established through nodes N N 6K3.

It is necessary that a preference be established for the nodes at eachlevel. That is, a preference must be established for each node at thatlevel with respect to every other node at that level. An example of thisis:

( i iz ix This means that, when establishing a connection through thenode array, at level i, N is preferred to N and N is preferred to N inestablishing a connection. Hence, in establishing a connection, N willbe used if it is not busy"; i.e., already part of another connectionpreviously established.

In the array as described above, connections of maximum length m can beestablished. This array could provide connections or chains of nodes inexcess of m in length simply by switching back through the nodalnetwork. A typical chain of this sort would be:

(3) N N N N N Self-addressing memory A system including a node arraywhich generates the sequence of addresses required for the storage ofthe words of a record is shown in FIG. 2. In such a system a source nodeis picked for each record. The address of this source corresponds to arecord address for this record and remains in that associationthroughout the lifetime of the storage of this record in the storagedevice. In order to select a particular source to be associated with aparticular record, the record address is connected to the source controlnetwork 201 which in turn picks one of a plurality of sources 202. Anexclusive connection is then established through a number of nodes inthe node network 203, one node being energized for each word of therecord read into the memory. The outputs of each of the nodes areconnected through a converter 204 to the memory address decoder 205. Theconverter 204 merely converts the energization of a particular nodeoutput into a code which can be accepted by the memory address decoderto allow the entering of a particular word into a particular storagelocation in a magnetic core memory 206.

The connections through the node network 203 are establishedsynchronously so that the connection is allowed to proceed to the nextlevel only after the newly selected node is gated to the memory addressdecoder 205 where the proper memory address is selected and thecorresponding word of the record is read into the magnetic core memory206 over an input 207. The electrical connection through the nodenetwork remains so long as the record remains stored in the magneticcore memory. When the source is turned oif, the connection is broken andthe nodes employed in the connection are, therefore, made idle. Thus,they are available for inclusion in other connections corresponding tothe storage of other records.

Determining the addresses of the words comprising a record which is tobe read out of storage is very similar to the process for developing theaddresses described above. The words are read out of the magnetic corememory 206 over an output line 208 as the node network 203 generates theplurality of readout signals, each corresponding to one of the nodes inthe connection associated with the particular record to be read out.

The node network 203 is under control of a node network control circuit209 which produces the signals necessary to write the record into orread the record out of the magnetic core memory. The node networkcontrol circuit 209 is under control of a write signal applied over theinput 210 or a read signal applied over the input 211. When the nodenetwork control circuit 209 is under control of a read signal appliedover the input 211, the network control signal will sequentially producea plurality of control signals designated read level 1', read level kread level m and so on. These sequential signals are applied throughread control circuit 212 to the node network 203. Simultaneously, withthe occurrence of each read level" signal, a spike generator 213produces a read spike which is applied through one of the sources 202which is associated with the record being read to the node network 203.Thus, when the first level of the node network 203 is being read, thesignal read level i is energized and simultaneously a read spike isconnected through the particular source 202 associated with the recordbeing read to the node network 203. The simultaneous application ofthese two signals to the first level in the node network energizes aparticular node in the first level and this node, acting throughconverter 204 and memory address decoder 205 permits a word to be readfrom the particular storage location in the magnetic core memory 206 orover the output line 208. The operation then proceeds with theoccurrence of the read level 1' signal and the occurrence of anotherreadout spike from spike generator 213. This causes the next level ofthe node network to be energized and another word to be read out ofmagnetic core memory 206.

The node network 203 is shown in more detail in FIG 3 which shows twolevels of the node network, each of which includes three nodes. Thefirst level, designated level 1', includes a node 301, designated N node302, designated N and node 303, designated N The sources are showndiagrammatically in FIG. 3 as being three position switches. Forexample, the source S includes a switch 304 which can be set to aposition 304a, 304b, or 3040. When the switch 304 is positioned on thecontact 304a, as shown in FIGURE 3, a voltage V is applied to thevarious nodes in the first level and this voltage maintains anyconnection which has been established through source S to one of thenodes in the first level. When the switch 304 is in the position 304b,the nodes associated with that source are in the open condition throughthese nodes. When the switch is in the position 304e, a read spike fromthe generator 305 is applied to the nodes at the various levelsassociated with sources 8,, and the nodes associated with this sourceare read.

Similarly, source S is shown diagrammatically as including the switch306 and source s is shown as including the switch 307. It should, ofcourse, be understood that the switches shown could be replaced byelectronic components for performing the switching functions of thesources.

In order to establish a preference for the selection of a particularnode in a level relative to the other nodes in that level in a givensequence of nodes at several levels, each node is interconnected withthe other nodes in that level. In the embodment shown, it is assumedthat node 302, N is preferred to node 303, N which is, in turn,preferred to node 301 N Therefore, three outputs from node 302,designated S S 7, and S are connected through lines 308, 309, and 310 tothe other nodes in level i. The negation of these three outputs willinhibit the selection of nodes 301 and 303 in a connection unless node302 is already in use, that is, it is busy. Similarly, nodes 301 and 303are interconnected with each other and with node 302 to completelyestablish an order of preference in the establishment of connectionsthrough level 1'.

Three control signals are also applied to the nodes of level i. Thefirst of these control signals, designated proceed to next level isapplied to nodes 301, 302 and 303 over the line 311. This signal occurscyclically and controls the advancement of a connection through thevarious levels of the node network. The signal advances the connectionthrough level i to the next level. A second control signal read level iis applied to all of the nodes in level i when it is decided to readinformation out of the memory. This signal is applied over the line 312to all of the nodes in level i. A third signal, designated reset FFs" isapplied over a line 313 to all of the nodes in level i and resets outputflip-flops in these nodes after the nodes have been used in any cyclefor reading information from the memory.

Each node has an output, the one from node 301 being over the line 314.The line 314 is connected through converter 204 to the memory addressdecoder and indicates the storage location into which information is toread or from which information is to be read. Similarly, the output fromnode 302 is over line 315 and the output from node 303 is over line 316.

The outputs from each of the nodes in level i are also connected to thevarious nodes in the next level, designated level j. Level j includesthe nodes 317, 318 and 319. The nodes of this level are interconnectedin the same way that the nodes of level i are interconnected and thesame control signals are applied to the nodes of level y.

Referring to FIG. 4, there is shown a logic diagram of a single nodewhich may be employed in the node network array. This node correspondsto the node N previously described. When the source S is energized, theline 401 is raised thus enabling AND gate 402. The other input to ANDgate 402 is a signal indicative of the negation of all signals whichmight inhibit the connection of node N in a connection. In order to formsuch a signal, the signals and S are applied to an AND gate 403. Thesesignals are indicative of the fact that source S has not previously beenconnected to either node N or N In either case, it would not bedesirable to put node N in a connection with source S Also, the signalsN set plus N set are applied to AND gate 403. These signals indicatethat nodes N and N are already set. Therefore, since the other nodes inlevel i are already set it is desirable to use node N in a connection.If either of these nodes, N or N were not set, N would not be used in aconnection since both N and N are preferable to N in making aconnection. The output of AND gate 403 is connected through OR gate 404to the other input of AND gate 7 402. When all of the conditions forestablishing node N as a node in a particular connection areestablished, the output of AND gate 402 is up. The output of AND gate402 is designated S This signal is inverted in inverter 405 which formsthe signal S and this signal is connected to other nodes in level i toindicate that S is connected to N The output of AND gate 402 is alsoconnected back through OR circuit 404 to the input of AND gate 402 sothat once the signal S is established it is locked-in through OR gate404. The combination and AND gate 402 and OR gate 404 is termed a latch.

The signal S is one of several inputs to an OR circuit 406 the output ofwhich is used to set a latch 420 to indicate that the node N isenergized or used in a connection. When the latch 420 is set, the memorystorage location associated with the node output line taken from thelatch 420 can be read to or written from. The output from OR gate 406 isalso inverted in an inverter 407 to produce the signal N set. Thissignal is applied to AND gate 403 and other AND gates in the node N toprevent N from being used in connection when it is already in use orbusy. The output of OR circuit 406 is connected through an AND circuit408 to form the output to the next level. AND gate 408 is energized onlywhen the output of OR gate 406 is up and the signal proceed to nextlevel" occurs. The output of AND gate 408 is connected back through ORgate 409 to the input of 408 to lock-in the output of AND gate 408 whenit occurs.

The output of AND gate 408 is also connected through an inverter 410 toan AND circuit 411. The output of OR gate 406 forms the other input toAND gate 411. Between the time that OR gate 406 produces an outputindicating the node N is to be included in a connection and the time atwhich the output to the proceed to next level signal occurs, the ANDgate 411 is energized thus producing an output which set latch 420.After the occurrence of the proceed to next level signal, the signalreset FFs" occurs which resets the latch 420.

An AND circuit 412 also provides an input to set the latch 420 in orderto read the information out of the memory when this is desired. Theoutput of AND gate 408 forms one input to AND gate 412 and the readlevel i signal forms another input to AND gate 412. The third input toAND gate 412 is from the spike generator. There will be a spike pulseinput to AND gate 412 only when the record which it is desired to readis associated with one of the sources connected to the node N If weassume that the record which it is desired to read is associated withsource S there will be a spike input to AND gate 412 from switch 304 andcontact 304a, FIG. 3, during read time. This spike passes through ANDgate 412 because the other inputs to AND gate 412 are up. That is, theoutput of AND gate 408 is up because node N is included in theconnection from source S and the signal read level i is up during thisread time. Therefore, the output of AND gate 412 sets latch 420 throughan AC. input to latch 420. The output line of latch 420 is then up andthe information contained in the storage location associated with node Nis read out. After read out time the reset FFs signal occurs and thelatch 420 is reset.

Two other sources, S and s are also connected to node N Source S isconnected through an AND gate 413 to form a second input to OR gate 406.The output of AND gate 413 is designated S indicating that node N isassociated with source S The other input to AND gate 413 is a signalindicative of the negation of any signals which would inhibit the use ofnode N in a connection involving source S In order to form such asignal, the signals S and the signals N set plus N set are applied to anAND gate 414. Also applied to this AND gate is the signal N set which isindicative of the fact that the node N is not already busy. The outputof AND gate 414 is connected through OR gate 415 to the other input toAND gate 413. The output of AND gate 413 is connected back through ORgate 415 to lockin the output of AND gate 413 once it is obtained. Theoutput of AND gate 413 is also connected to an inverter 416 whichproduces the signal S Similarly, the source S is connected through anAND gate 417 and associated circuitry to form the third input to OR gate406. Therefore, the node N can be associated with either S S or S Theoperational sequence for writing a record into the magnetic core memory206, shown in FIGURE 2 is as follows:

First, the reset FFs line is raised thus resetting all of [he latchessuch as the latch 420 in node N Next, an available source is selectedwhich is to be associated with the record to be written into the memory.Next, the proceed to next level line is raised. This allows one of thenodes in the first level to be selected in accordance with theavailability of the nodes in that level and in accordance with thepreferences established for the selection of nodes of that level. Uponthe occurrence of the proceed to next level signal, the output latch inthe node selected is set and the first word of the record is enteredinto the storage location associated with that node. Next, the reset FFsline is raised thus resetting the latch in the selected node. Thisprocess is then repeated for the next word of the record which is to beentered into a storage location. The process continues until all of thewords of the record are entered into storage locations in the magneticcore memory.

The operational sequence for reading a record out of the magnetic corememory is as follows:

First, the reset FFs line is raised. Next, the source corresponding tothe record to be read out is selected. Next, the read level 1' line israised. Next, a voltage spike is put on the source line corresponding tothe record which is to be read out. This sets the latch for the node ofthe first level corresponding to the connection which has beenestablished for the record being read The output line of this nodeenables the particular storage location associated with this nodethrough the memory address decoder, and that word is read out. The resetFFs line is again raised. The process is repeated with the exceptionthat during the next cycle the read level 1' line is raised. The processcontinues with each level being raised until the record is completelyread out of the several memory locations in which are stored the wordswhich comprise the record. The source is then disconnected if the recordis not to be read out again. If the record is to be read outrepetitively the source is not disconnected.

Under certain circumstances it is desirable to include a particular nodein a connection regardless of the preferences existing among the variousnodes of that level. A slight modification which makes this possible isshown in FIG. 5 in which like numerals refer to the similar circuitry ofFIG. 4.

Referring to HO. 5 there is shown how the general node circuit of FIG. 4is modified to permit the establishment of a unique connection from anysource node to any given node, if available, in the network. Themodification includes a hold goal" signal which is applied to AND gate508 through an inverter 509. The hold goal line is activated only untilthe connection, terminating in this node, is established throughintervening available nodes. The actuation of this line permits the nodeto enter into a connection regardless of whether it may be lesspreferable than any one or all of the other nodes of its level. Thenegation of all other hold goal lines for this level are ANDed togetherto inhibit the establishment of the goal seeking connection to this goalif it is not the goal node regardless of whether it may be preferred tothat node in normal establishment of the sequence. That is, the signalsN goal and N goal are negated and applied to AND gate 503 to inhibit theestablishment of a connection through this goal if it is not the goalnode.

The goal seeking connection is established just like any otherconnection in the write sequence already described. The addition to thisis that the right hold goal line must be activated at least until thegoal is reached, that is, the connection is established. Read out isaccomplished in the same manner as described above.

Several connections of this nature could be established one after theother, one at a time. Thereby, nodes on successive levels can beestablished into a chain simply by considering each one to be a goalsuccessively until all of the nodes are established in one chain. Theline labeled hold goal in FIG. 5 is actuated during the period in whichthe proceed to next level signal is applied to the nodes of this levelto propagate some other connection such that this connection will notalso try to propagate itself and thereby interfere with the connectionsbeing properly established.

In FIG. 5 there is also shown a signal labeled make N busy. Thisrepresents another modification of the circuit shown in detail in FIG.4. If both this line and the hold goal line are simultaneously actuated,this node will be made unavailable for its inclusion in a connectionthrough the network. Such a node is termed a busy node.

One circuit which may be used to implement the node logic diagram ofFIG. 4 is shown in FIG. 6. The circuit shown in FIG. 6 utilizes A.C.magnetic amplifiers including ferrite cores which are saturated with DC.applied on appropriate windings. The input from source S is an A.C.signal which is applied to a winding 601 on the ferrite device 602. TheA.C. input signal will be coupled through to an output winding 603 onlyif the ferrite device 602 is unsaturated. The ferrite device 602 isdriven to saturation if any one of the signals S applied to winding 604,S applied to winding 60S, N,- set, applied to winding 606 or N setapplied to Winding 607 is up. Once the signal S is coupled to the outputWinding 603, it is applied through a diode 608 and a resistor 609 to aholding core 610. The A.C. signal S is rectified in the diode-resistorcombination 608, 609 and applied to the winding 611 on the holding corein such a manner as to overcome the bias applied to the holding corethrough bias winding 612. When this occurs the signal S is coupled fromwinding 613 through the holding core to the output winding 614.Therefore, once the signal S is coupled through the core 602, it willremain coupled to the output through a holding core 610. The signal S isthen connected to a windinw 615 on the output ferrite device 616.

The input signal 8;; is similarly coupled through an input core 617 andholding core 618 to the winding 619 on output core 616. Similarly, thesignal from the source S is coupled through input core 620 and holdingcore 621 to winding 622 on the output core 616. The output core 616serves as an OR circuit in that a signal on any one of the windings 615,619 or 621 will be coupled to the output winding 623. The output coreserves as an AND device in that there will be an output only if theadvance to next level signal applied to winding 624, is present toovercome the saturating bias applied to winding 625. When an output isproduced on the winding 623 it is rectified in the diode 626 andresistor 627 and applied to the holding winding 628 so as to hold theoutput core 616 in the unsaturated condition. The output is alsoconnected to a winding 629 on the indicator core 630. When the outputsignal is present the signal winding 629 overcomes the saturating biasapplied to winding 631 so that the indicator core 630 can couple a turnout signal from winding 632 through to winding 633 which will in turnenergize the indicator 634. The output is 10 also connected throughwinding 629 to biasing windings 635, 636, and 637. When the node isenergized, the rectified output signal applied to windings 635637saturate the ferrite devices 602, 617 and 620 to prevent other sourcesfrom energizing the node.

Buflcr-storage device The use of the sequential decision making deviceof this invention for assigning buffer storage space in a computersystem is best explained in conjunction with FIGS. 7, 8a and Sb. Thesystem shown in FIGS. 7, 8a and 8b serves as a butler between severaldata transmission lines and a digital computer which both receives datafrom these lines and transmits data out 0 er such lines. In such asystem it is quite desirable that messages transmitted over the linesneed not be of a definite length. In such a system there must be somemethod of allocating the butter storage space in a single buffer whichservices all of the transmission lines. The sequential decision makingdevice of this invention provides the means for allocating the storagespace in a single buffer unit.

Referring to FIG. 7, there are two sources associated with eachtransmission line. That is, a source 701, designated S and a source 702,designated S are associated with input line I. Similarly, a source 703,designated S and a source 704 designated S are as sociated with inputline N. Each of the sources is of the type previously described. Thatis, each source can be turned on or turned off. All of the sources areconnected to the node array 705 which is of the type previouslydescribed. While only input lines I and N have been shown, it will, ofcourse, be understood that any number of input lines could be provided.

Each output line is similarly associated with two sources. The outputline I is associated with source 796, designated 8 and source 707,designated 5 Also, output line N is associated with source 7tl8,designated S and source 709, designated S The sources 706-709 are alsoconnected to the node array 705.

Each input line has four possible statuses. The first possible status isthat a message is being received. Under these circumstances the sourcesassociated with the input line are being used as an identity point for amessage presently being accumulated in the buffer from the transmissionline. The computer cannot select this source in order to send out amessage while it is in this status.

The second possible status for an input line the message ready status.In this case the message for Which this source serves as an identitypoint has been received in full from the transmission line and may beread out by the computer. The computer can scan sources which are inthis status whenever it is ready to ingest messages.

The third possible status for one of the input lines is the not selectedstatus. In this case the source is not selected and is not serving as anidentity point for a message either arriving or which has arrived on it.

The fourth possible status for an input line is the message being readstatus. In this case the source was in the message ready status and hasbeen selected by the computer in order that the message for which itserves as an identity point may be read into the computer forprocessing.

Similarly, the output lines have four possible statuses. The firstpossible status for an output line is message being transmitted status.In this status, the sources associated with the output line are beingused as an identity point for a message presently being transmitted fromthe buffer onto this transmission line. The computer cannot select thissource in order to use it as an identity point for a message which itdesires to dispatch onto this transmission line.

The second possible status for an output line is the message readystatus. In this case the message for which the source serves as anidentity point has been received from the computer and is ready fortransmission on the line serviced by this source. This status is reachedby the inclusion of an end of message character in the message. The endof message character was written into the message by the computer. Thisis a transient status which proceeds to a message being transmittedstatus unless acknowledgement by the transmission equipment to a requestto transmit signal from the source equipment is required prior todispatching the message onto the transmission line.

The message being written status indicates that the sources associatedwith a particular transmission line were in the message ready status andnow the message for which the source serves as an identity point isbeing transmitted from the computer to the buffer.

The fourth and final status for the output lines is the not selectedstatus. The source associated with particular output line is notselected as an identity point for holding a message to be transmited.

Referring to FIGS. 8a and 8b there is shown a system for assembling anddisassembling messages from an input line 881 and an output line 802.The system of FIGS. 8a and 8b serves as a butter between these input andoutput lines and a computer 803. It should be understood that variousother input and output lines could be handled by this system and theother input lines are shown schematically as input line 804 and outputline 805.

Input line 801 is connected directly to a one word data register 806.Each word from the input line 881 is transferred from the data register865 over line 807u 8871) into the butter register 808. The word istransferred from butter register 808 into the magnetic core memory 809.This transfer is accomplished under control of node network 810 whichacts through the memory address decoder 811 and the memory addressregister 7 812 to transfer words of information from the butler register808 to the magnetic core memory 809.

When a word is received in data register 806 from input line 881 theline 813 is raised indicating that the first word of a message isreceived. This line 813 is be temporarily stored in the magnetic corememory. T

The command to scan for input line service requests is received overline 818 from the buffer cycle priority control circuitry 819. When thewrite cycle request scanner scans an input indicating that one of theinput lines has an input word ready to be written into memory, the writecycle request scanner 817 produces a signal indicative of theidentification of the requesting input line. This signal is transferredover the line 828 which connccts this identification signal to thebuffer cycle priority control circuit 819. The butler cycle prioritycontrol 819 then acts through the write cycle control 829 and the timingand driving circuits 821 to gate the input message into the magneticcore memory 809.

The particular storage locations into which the input mensage is to begated is controlled by node network 810.

When the write cycle request scanner 817 determines that the input line801 has a message which is to be read into the magnetic core memory, anoutput is produced over line 822 which enables an AND gate 823. Theother input to AND gate 823 is from the line 816 which is up because aword is in the data register 886. Accordingly, AND gate 823 produces anoutput which is connected over line 824 to the sources 814 and 815. Whenthe line 824 is up, a write cycle is being performed upon input line891. This write cycle is also controlled by the node network controlcircuitry 825 which is the same type of circuitry as previouslydescribed.

The last word in each input message is an end-ofmessage word. This wordis sensed by an end-of-message sensor 826. The end-of-message sensor 826produces an output on line 827 indicating that a message is ready foruse by the computer. This and other similar input lines are scanned byan input message ready scanner 828. The input message ready scanner 828scans all of the inputs under the command of the computer 803 whichsends out a command over the line 829 commanding the scanner 828 to scanfor messages. When the scanner 828 notes a ready message, the address ofthe input line which is transmitting the message is transferred to theline address register 830. Under command of a read line address commandover the line 831 to the AND gate 832 the line address is transferredfrom the line address register 830 over the line 833 to the computer803.

When the computer is ready to ingest one of the messages which has beenstored in the magnetic core memory, the computer transfers the inputline address over the line 834 to the input line address select circuit835. This circuitry is connected to a read cycle request scanner 836which, under control of a command transferred over the line 837, willscan all of the inputs for read cycle requests. When the read cyclerequest scanner notes the request to read a particular message, therequesting line identification is transferred from the read cyclerequest scanner 836 to the butler cycle priority control 8159. Thebuffer cycle priority control 819 acts through the read cycle control837 and the timing and driving circuits 821 to transfer information outof the magnetic core memory.

The addresses of the storage locations in the magnetic core memory 809which are to be read out are determined by the node network 810. If theread cycle request scanner determines that the message ingested over theinput line 801 is now to be read out, both inputs to the AND gate 838are raised. The output of AND gate 838 is connected to sources 814 and815 and determines that the storage locations in the magnetic corememory 809 which are associated with nodes which are in the connectionsfrom sources 814 and 815 will be read out. These storage locations areread out through the buffer register 808 over the data line 839, throughthe register 840 to the computer 803. The register 840 is included inthe data line to provide temporary storage so that there is no delay inthe transfer of the data if the message cannot be immediately used. Anend-ofmessage sensor 814 is provided to provide an indication to thecomputer when the complete message has been read out of the magneticcore memory into the computer.

When the computer is ready to transfer a message to the magnetic corememory for later transmission over one of the output lines, the addressof the output line is transferred over line 842 to the output lineaddress select circuit 843. The output of this circuit is also connectedto the write cycle request scanner 817. Upon scanning all of the inputs,if the write cycle request scanner 817 notes that the computer is readyto write a mes sage into the magnetic core memory for later transferover output line I, the write cycle request scanner raises the line 844which forms one input to an AND gate 845. The other input to AND gate845 is from the output line address select circuit 843. When both of theinputs to AND gate 845 are raised, the output of AND gate 845 energizesthe sources 847 and 848. The sources 847 and 848 establish connectionsthrough the node network 810 to control and determine the storagelocations to which the computer is to transfer data. This transfer ofdata takes place over the data line 848, through the temporary storageregister 849 and the butter register 868 to the magnetic core memory809. An end-of-message sensor 850 senses the end-of-the-message which isbeing transferred from the computer to the magnetic core memory.

When the message is transferred from the computer to the magnetic corememory the first word of the message is transferred over the lines 851aand 851)) to the word data register 852 associated with output line Iover which the message is to be transmitted. The word data register 852is connected to the AND gate 853 which when energized produces a readcycle request signal which is connected over line 854 to read cyclerequest scanner 836. When the read cycle request scanner 836 determinesthat this particular input indicates that a message is ready to betransmitted over output line 1 the read cycle request scanner enablesthe AND gate 855 the ouput of which is connected back to nodes 847 and848. These sources then connect all of the nodes which are associatedwith the storage locations containing the message to be transmitted overoutput line I. The message is transferred under control of the nodenetwork from the magnetic core memory, through the buffer register 808,over lines 852a and 85th, through the one word data register 852 and outover output line 802. When the last word of the message is transmittedfrom the one word data register 852, the end-of-message sensor 856senses the last word and enables an AND gate 857 which then disconnectssources 847 and 848 from the connection and makes them available for thetransmission or reception of another message.

Task ordering device The sequential decision making circuitry of thisinvention used as a task ordering device in a computer is described inconjunction with FIGS. 9-16.

The sequential decision making circuitry of this invention can be usedin a multi-programrned computer in which several programs proceedindependently of each other to carry out the various tasks of eachprogram. That is, each program is written in complete disregard of anyother program or programs with which it might have to share thefacilities of the computer system. In general, a computer system towhich such a system might be applied is shown in FIG. 9. Referring toFIG. 9, the computer includes a plurality of input-output units, forexample, 991 and 902; a plurality of arithmetic and logical units, forexample, 993, 904, and 905; and a plurality of memories, for example,906, 907 and 908. All of these units may be used simultaneously orsequentially to carry out a plurality of computer programs. These unitsare assigned various tasks in the programs by the sequence andinformation routing control circuit 909. The sequential decision makingcircuitry of this invention performs the function of the sequence andinformation routing control circuit 909.

Each independent program is designated a task sequence which includes anumber of tasks, A, B, C, etc., which must be performed in a prescribedsequence such as: first task A, then task B, then task C, and so on.Each task might for example, represent a subroutine in the computer.Further, the task could correspond to a particular unit of the computersystem such as arithmetic and logical unit 903 in FIG. 9. Then the tasksequence would represent the necessary time sequence of operations whichmust be performed by the computer system in executing the overallprogram. As a concrete illustration of a system, it will be assumed thatthe system has ten selectable tasks which are designated A, B, C K. Itwill also be assumed that the system can handle any sequence of thesetasks with a maximum length of seven tasks. This can be representedschematically by the program array shown in FIG. 10. In 10, AK representten selectable tasks which can be performed during any one of timeintervals I, through r Each of the nodes in FIG. 10 corresponds to asub-routine stored at a sequence of addresses beginning at the memoryaddress corresponding to this node. Each node in this circuit consistsof several subnodes each of which is similar to the circuit shown inFIG. 6. That is, there are several possible paths through a given nodepoint in the array. Each task sequence which employs the task controlledor represented by a particular node is connected to it by means of oneof the several submodes which constitute this particular node. Forexample, in FIG. 10, task sequence I includes the task A at time 1;, thetask B at time 1 the task B at time r the task C at time 12; and thetask C at time 2 This is the end of task sequence I. Task sequence IIincludes tasks A, C, D, C, B, C & E in that order.

Intranode preferences can be set up such that should two task sequencesbe connected through the same node point simultaneously the tasksequence connected to the sub-node having the greatest connectionpreference will get control of the function related to that node first.Subsequently, of course, the task sequence having the lesser preferencefor this node will be able to make its request for services by the taskrepresented by this node.

Prior to the execution of the task sequences to be performed, each tasksequence is set up by linking the connection establishing sub-nodes ateach stage in the node array. Thus, for task sequence I the followingconnection among connection establishment sub-nodes are made. Task Athrough Task B through Task B through Task C through Task C. Theoperation of the scquential task ordering device based upon the nodenetworks described previously is as follows: Each task sequence proceedsstage by stage to completion. At completion of the task sequence, theconnections through the subnodes are broken unless it is desired torerun the program corresponding to this task sequence again. Conflictswith other task sequences for computer system facilities at each stageare resolved at each stage where this problem is encountered. At suchpoints of juncture, that is, at a stage at which two task sequencesrequire the use of the same facility and both sequences request the useof this facility simultaneously, the conflict can be resolved on eithera first come, first serve basis and/or by a priority scheme. A tasksequence could be given an absolute first preference, an absolute secondpcrferencc or uniform preference, that is first come, first served, withregard to the other task sequences that might be simultaneouslycontending for the use of a particular task function. In this typeoperation, the completion of a task at a particular stage will cause astart function signal at the node of the next stage which is a member ofthis task sequence. This start function signal will cause this task tobe performed provided that there are no simultaneous requests for thistask by other sequencies to which a higher preference has been given.

In a more sophisticated system the sequential task ordering device andthe computer in general may be controlled by a master control program.With this mode of operation the function completed signals for each taskcause a node in another array called the control scanner to beactivated. The control scanner is shown diagrammatically in FIG. 11.FIG. 11 shows the broad concepts of the control scanner which is shownin more detail in FIGURES 12 and 13. The control scanner consists of twobasic parts, a service request array and a control array. When afunction completed signal for a given task is turned on, regardless ofwhich sequence or what stage this function is a part, the correspondingnode in the service request array is turned on. The particular node, ofthe eleven possible in this example, which is turned on is that nodewhich comes at the time level next in sequence. For example, if sixnodes had already been turned on, then if a task B gave a functioncompleted signal the node at position B-Tq would be turned on oractivated.

When the computer is ready for a master control cycle, that is, it isready to set up a sequence of tasks it must perform, it gates the firsteight of the eleven positions of the service request array into thecontrol array. The number of stages, eight in this example, in thecontrol array is made equal to the number of jobs the computer must havelined up to perform at any one time.

The activated nodes in the control array shown in FIG. 11]) are linkedtogether electrically in the manner described in conjunction with FIG.5. That is, each activated node is made a goal successively until alleight of the activated nodes are linked together. A node correspondingto a particular task to be performed would be selected as a goal. Aconnection would be established to this goal in the manner describedabove. The nodes forming this connection would correspond to theintermediate tasks which must be performed prior to the designated task.Each of these nodes could likewise correspond to a program in acomputers memory which must be performed before the goal or task programis executed.

When a goal is selected, as described above, nodes corresponding toprograms which are not to precede the attainment of this goal are madebusy as described above. The remaining available nodes would thereforecorrespond to possible intermediate tasks in the possible alternatepaths available to achieve this desired goal. Further, note that certainnodes which are suitable for inclusion in a connection to this goal nodemay be busy due to their inclusion in a previously establishedconnection. This could be symbolic of either a particular programs beingin use or a particular device, such as an arithmetic unit, orinput/output unit being operated in connection with another tasksequence.

The various levels in the node network (see FIGURE 1) correspond to theprecedence relations existent among the several nodes. For example, anytask level i will be executed prior to any task in level 1'.

A program control system utilizing the sequential task orderingtechniques of this invention is shown in FIGS. 12 and 13. The systemincludes a program array 1201, program sources nodes 12021205, a programtask sequence setup register 1206, a service request array and controlarray formed into one three dimensional array 1301, and various functioncontrols 1302-1311. The program control system also includes the controlcircuitry necessary to operate this equipment.

The operation of the program control system is as follows:

(a) Program setup Each task sequence is read into the program setupregister 1206. The program setup register has a plurality of stagescorresponding in number to the number of stages of the program array.There is a corresponding stage of the program setup register for eachstage of the program array. Each such stage of the program setupregister 1206 is divided into two sections. For example, 1207 and 1207aform the first stage, 1208 and 1208a form the second stage, and so on.The first section of each stage holds the indication of the particulartask to be performed in this sequence at this stage. The second sectionof the stage holds the priority of this sequence for this task at thisparticular stage relative to other sequences which might select thisstage. That is, stage 1207 indicates that the Task A is to be performedat this level. Section 1207a indicates that this task is to be givenfirst preference at this stage. Similarly, stage 1208 indicates tht taskB is to be performed at this stage while section 1208a indicates thatthis task is to be given second preference.

The preferences are indicated as follows:

First preference-1;

Second preference2;

First come, first served; no preference-3;

Stage not selected for inclusion in this task sequence0.

In order to initiate the performance of a particular task sequence, oneof the program source nodes 12021205 which will serve to identify thistask sequence is put into the select mode of operation.

(b) Program army The program array 1201 contains one node corre spondingto each selectable task at each stage of the array. The details of theprogram array are shown in FIGS. 14 and 15. Each node of the programarray is subdivided into a number of sub-nodes, there being one sub-nodefor each preference level. In the example shown in FIGS. 14 and 15 it isassumed that there are two levels of preference and hence two sub-nodesfor each node. As shown in FIG. 14 there are two nodes corresponding totask sequence A and task sequence B at level 1 A typical firstpreference sub-node and a portion of a second preference sub-node of theprogram array is shown in FIGS. 14 and 15. As shown in FIG. 14 a selectcore 1401 and a hold core 1402 are provided for the source S input tothe sub-node and a select core 1403 and a hold core 1404 are providedfor the source S input to the suhnode. It will be understood, of course,that as many pairs of select and hold cores as there are sourcesrequiring the use of this sub-node will be provided.

Referring to FIG. 15, a first preference core 1501 is provided andproduces an output which connects the subnode in the particular tasksequence given first preference. Similarly, a second preferance core1502 is provided and connects the sub-node in the task sequence givensecond preference. If the system is to be provided with more than twopreference levels then additional preference cores should be provided.The output lines from the sub-node are ORd together into a request core1503. Request for service from second preference, and lower preference,sub-nodes will not be permitted to operate the request core until therequest of the first preference, and all order of preferences greaterthan the given one, have been satisfied.

The task sequence is loaded from the program setup register 1206 intothe program array 1201 as follows. The sections of the program setupregister 1206 which designate the task to be performed energize thecorresponding task select line. For example, assuming that the sub-nodeshown in FIGS. 14 and 15 is associated with task A, then stage 1207 ofthe program setup register 1206 energizes the line 1405 designated taskA select.

Similarly, the program setup register stage which designates thepreference of the task at this stage energizes the correspondingpreference sub-node select line. For example, the section 1207a holds afirst preference and this section of the stage energizes the line 1406designated first preferance sub-node select.

Energization of a task select and a preference select line for aparticular select core causes the corresponding hold core to pass theA.C. hold voltage from the given program source node to the output. Forexample, if lines 1405 and 1406 are energized, the A.C. voltage from theparticular source node, that is, either from source S over input line1407 or from source S over input line 1408, will pass through the selectcore to the hold core. Therefore, if source S is associated with theparticular task sequence which is being set up the A.C. hold voltagewill pass from input line 1407 to the select core 1401. The A.C. holdvoltage will be coupled from the winding line 1409 to output winding1410 because of the A.C. voltage applied to input lines 1405 and 1406thus keeping select core 1401 out of saturation. The A.C. hold voltagefrom output winding 1410 is rectified by diode 1411 and applies anunblocking bias to hold core 1402 thus taking the hold core 1402 out ofsaturation. Because of this, the hold voltage from input 1407 is coupledfrom input winding 1412 to output winding 1413 and this couplingcontinues even though the D.C. voltages are removed from input windings1405 and 1406. That is,

1. A COMPUTER CONTROL SYSTEM ESTABLISHING A SEQUENCE OF CONTROL SIGNALSCOMPRISING A PLURALITY OF NODE CIRCUITS EACH OF WHICH PRODUCES ONE OFSAID CONTROL SIGNALS WHEN ENERGIZED, SAID NODE CIRCUITS BEING ARRANGEDIN LEVELS, MEANS FOR INTECONNECTING THE NODE CIRCUITS IN EACH LEVEL INSUCH A MANNER AS TO ESTABLISH A PREFERENCE IN THE ENERGIZATION OF NODECIRCUITS IN THAT LEVEL, MEANS FOR SEQUENTIALLY ENERGIZING ANDINTERCONNECTING ONE NODE IN EACH LEVEL WITH A NODE IN ANOTHER LEVEL INACCORDANCE WITH THE PREFERENCE AMONG UNENERGIZED NODES IN THE RESPECTIVELEVEL, MEANS FOR MAINTAINING SAID SEQUENCE OF NODES IN THE ENERGIZEDCONDITION TO PERMIT THE SUBSEQUENT REPRODUCTION OF THE SEQUENCE OFCONTROL SIGNALS PRODUCED BY SAID ENERGIZED NODES AND MEANS RESPONSIVE TOSAID SEQUENCE OF CONTROL SIGNALS FOR PERFORMING A DESIRED COMPUTERFUNCTION.